1. Field of Invention
The invention relates to a packaging structure used in IC (integrated circuit) chip packaging. In particular, it relates to a packaging structure with low switching noises.
2. Related Art
To meet the high frequency and high-speed demands for high-tech products, the rise time of a circuit system becomes even faster. At the same time, this makes the timing budget and noise margin tighter than ever. In addition to device selections, the system stability has definite influence on noise immunity of the circuit. The three major subjects in noise suppression are reflection noises, coupled noises, and switching noises.
Impedance matching is important for the reflection noises. For the coupled noises, it is essential to notice the control of the distance and length of parallel wires. The switching noises or SSN""s (simultaneous switching noise) generated when a high speed IC turns on and off and requires a tremendous amount of decoupling capacitors or bypass capacitors to stabilize the power supply and to filter high-frequency noises.
However, many capacitor elements are not compact and light enough for most of modern electronics. Furthermore, the longer a circuit loop is the more noises there are. Therefore, these capacitors have to be within a fixed distance from the IC (the faster the rise time is, the shorter the distance is required). That is, even if the substrate area is enlarged to accommodate more capacitors, it is still possible that the distance is too far to achieve expected effects. This is a problem for circuit designers.
Although the packaging sizes of passive components become smaller, SMD""s (surface mount device) changes from1210xe2x86x921206xe2x86x920805xe2x86x920603xe2x86x920402 to even 0201. Nevertheless, as the area gets smaller, possible capacitance also gets smaller. It is not easy to package a capacitor with a large capacitance into s small size. Moreover, it is not only complex to design a layout with many capacitor elements on a substrate, the small elements also cause great difficulty in surface bonding processes.
Nowadays, it is still hard to minimize independent capacitors with larger capacitance. As mentioned in the previous paragraph, the surface bonding process in this case is also difficult. Since large capacitance requires a large area of conductive plane; therefore, if the capacitor is integrated into the design of an IC wafer, it must occupy a large area on the wafer. This is very uneconomical. However, for higher and higher work frequencies, it will be even more difficult to restrain switching noises within an acceptable range if no capacitors with appropriate capacitance and number can be provided to IC""s.
To minimize the area occupied by passive components, a current method is to use embedded passive components. Although the built-in-substrate technique of using embedded capacitors in an organic substrate can achieve the high-density objective, the organic substrate has to use other high dielectric constant material. This specially prepared substrate does not only cost higher due to its complicated circuit board, the circuit layout is also very difficult. Since the dielectric constant of the material affects the area occupied by the embedded capacitors (i.e. the area has to be increased if the dielectric constant is not high enough), the area is often too big to be practical. (Ceramic substrates have a dielectric constant of about 9.5 and the commonly seen FR-4 has a dielectric constant of 4.7. To make the products more practical, the dielectric constant has to be more than 100.) Furthermore, most of the system substrates adopt cheap and widely used organic substrates (such as FR-4). However, materials compatible with organic substrates and dielectric constants high enough to be used as capacitors are still under development. The above-mentioned problems are the bottleneck of current embedded capacitor technique for organic substrates.
To solve these problems, some solutions had been proposed in the prior art. For example, the U.S. Pat. No. 5,633,785 utilizes an interconnect substrate with resistance, capacitance and inductance effects. The interconnect substrate is connected with a chip by wire bonding. The substrate is divided into an array of a plurality of blocks. Each block contains a passive component that can generate resistance, capacitance and inductance effects. Traces are used to connect each block to a bond pad outside the array. Although this provides a high-efficiency and high-density IC packaging method, the traces will generate unnecessary inductance effects to lower the quality of the circuit. Moreover, the design varies for different chip sizes and pin assignments. Therefore, it is very uneconomical.
In view of the foregoing, the invention provides a packaging structure with low switching noises. In this structure, a chip capacitor is directly connected to the chip, removing discrete SMT(surface mount technology) capacitor component and subsequent processing. The chip capacitor can be closer to the chip, providing better noise filtering effects. Since the chip capacitor and the chip are stacked together, the chip capacitor does not occupy extra area as independent capacitors. Moreover, the chip capacitor can have different capacitance values to satisfy different needs in circuits, so they are not restricted to any particular chip.
The disclosed packaging structure with low switching noises includes an IC chip and a chip capacitor. The chip capacitor is a capacitor structure with a plurality of electrode layers and insulation materials that have high dielectric constant. Each electrode layer has an I/O connect pad connecting to a top layer. The I/O connect pads of electrodes with different potentials are separate. The chip capacitor is then connected to a top surface or a back surface of the chip. The connection of the I/O connect pad on the IC chip and the chip capacitor is achieved through wire bonding, bumps, side conductors, pads or conductive through holes. The connection with the substrate is the same.
The I/O connect pad is an I/O bonding pad. Its shape can be a hexagon hive or other geometric patterns such as circles and quadrilateral. The I/O bonding pads of different electrode layers are arranged in an interposed way. This configuration provides a universal capacitor for all kinds of IC chips. The I/O connect pad can also be designed to surround the border of the top layer of the capacitor. Since it is a large-area contact, such a configuration an lower possibly unnecessary inductance effects.